module IFID(CLK, reset,
	    pc_in, pc_out,
	    instruction_in, instruction_out,block);

   input CLK,block;
   input reset;
   input [31:0] pc_in;
   reg [31:0]   pc;
   output [31:0] pc_out;
   assign pc_out = pc;


   input [31:0]  instruction_in;
   reg [31:0]    instruction;
   output [31:0] instruction_out;
   assign instruction_out = instruction;


   always@(posedge CLK or posedge reset)
     begin
        if (reset) begin
           pc <= 0;
           instruction <= 0;
        end else if (block) begin
           instruction <= instruction;
        end else if (!block) begin
    	   pc <= pc_in;
    	   instruction <= instruction_in;
     	end
     end

endmodule
